The present invention relates generally to semiconductors and more specifically the invention pertains to a circuit for semiconductor dynamic random access memory (DRAM) cells which is an improvement on previously known two-transistor cells by requiring fewer access terminals and permitting more compact layout of the cells.
My previous U.S. Pat. Nos. 3,513,365 and 3,634,825 describe two-transistor DRAM's which can be used as crosspoints, as non-destructive readout DRAM or, by using two cells per bit, as associative memory. The design and operation of those cells required two or three connections in the word direction of an array and one connection in the data direction for each cell. The present invention is an improvement over my prior patents in that it is capable of performing the same functions of the prior art while permitting a more compact layout of the integrated circuits, thereby providing a reduction in size of the circuits.